1. Field of the Invention
The invention relates generally to plasma etching in integrated circuit fabrication. In particular, the invention relates to a cleaning step performed prior to a dielectric etch step.
2. Background Art
Modern integrated circuits contain many levels of metallization, each including a dielectric layer separating one level of horizontal wiring from another. As illustrated in the cross-sectional view of FIG. 1, a lower layer 10 includes conductive features 12 at its surface needing to be electrically contacted from above. The lower layer 10 may be a dielectric layer in which the conductive features 12 are metal features, or it may be the silicon substrate in which the conductive features are doped regions of the silicon forming part of an active device. In order to increase the number of active devices and allow for complex wiring, the conductive features 12 have small lateral size and are packed closely together. An inter-level dielectric layer 14 is deposited on the lower layer 10. The dielectric layer 14 is typically formed of a silicon oxide deposited in a plasma CVD process using TEOS as a precursor, but more advanced dielectrics with low dielectric constants are being developed. The inter-level dielectric layer 14 typically has a thickness of about 1 xcexcm. The photolithography required for etching the contact and via holes through the dielectric often requires that the dielectric layer 14 be covered by a thin anti-reflective coating 16, commonly referred to as ARC. It maybe composed of BARC, a silicon-containing organic material, and have a thickness of 50 to 80 nm. However, inorganic ARCs, for example, of silicon nitride, are also well known. A photoresist layer 18 is deposited over the anti-reflective coating 16 and is photographically patterned to form mask holes 20,22. The smaller mask holes 20 correspond to the width and location of to via or contact holes to be etched in the dielectric layer 14 to contact the conductive features 12. The anti-reflective coating 16 has a thickness and refractive index that are selected to minimize extraneous scattering of the patterning light, which would degrade the resolution of the photolithography of the smaller mask holes 20. This description of the dielectric layer 14 is overly simplified. It may further include an etch stop layer at its bottom, and in complex interconnect schemes like dual damascene another etch stop layer vertically separates two parts of the dielectric.
After the photomask has been defined, the wafer is placed into a plasma etch reactor to etch contact or via holes 24, illustrated in the cross-sectional view of FIG. 2, through openings in the anti-reflective layer 16 and the dielectric layer 14 to expose the underlying conductive features 12. Either a contact hole or a via hole may be referred to as a plug hole. The contact or via holes 20 are then filled with a metal, such as aluminum, copper, or tungsten, to provide a vertical electrical connection through the dielectric layer 14 to contact the lower conductive features 12 to a horizontal electrical arrangement defined above the dielectric layer 14. This process may be repeated five times or more for advanced integrated circuits having multiple levels of metallization.
For advanced devices, the contact or via holes 24 are typically rectangular or square having a minimum width for advanced devices of 0.25 xcexcm or smaller and requiring a highly anisotropic etch to produce holes having a high-aspect ratio.
The larger mask hole 22 in the photoresist layer 18 defines through the dielectric layer 14 one or more open pads 26. The larger mask hole 22 is etched at the same time as the contact or via holes 24, according to the same etching process. The open pad 26, which can alternatively be called a monitoring area, is also typically rectangular or square and has significantly larger lateral dimensions than do the contact or via holes 20, by, for example, a factor of at least 50. A lateral dimension of 20 xcexcm is typical. The open pad 26 is usually located in an area of the chip or wafer not associated with the active devices and does not form a functional part of the integrated circuit being fabricated. It is called an open pad because it resembles a pad used for electrically contacting a bonding wire or other external electrical contact to the integrated circuit, but an open pad is never used as a contact. Indeed, open pads are typically formed in each level of metallization to monitor deposition and etching conditions for each level.
Because of its large size, the open pad 26 is more easily imaged than the very small contact and via holes. For example, etch rate and residues can be optically imaged in the open pad 26 while corresponding measurements in the narrow contact and via holes 24 typically require destructive sectioning of the wafer and time consuming electron microscopy. While open pads are particularly useful in developmental work, they also are frequently used in a production environment to assure that the standardized etch rates are being maintained.
Microloading effects are well known in which the aspect ratio of holes being etched and even the density of high aspect-ratio holes influence the etching rate. While microloading complicates the correspondence between etching rates of the narrow contact and via holes and of the much wider open pads, as long as the differences are small and fixed, a usable correlation can be obtained by applying empirically obtained proportionality factors.
Etching of the closely spaced, high aspect-ratio contact and via holes in the oxide dielectric requires an anisotropic etch. Further, the oxide etch should be highly selective to both photoresist and to silicon nitride etch stop layers defining the end of the etching profile. Such requirements have necessitated refinements in etching processes and plasma reactors. A particularly successful oxide chemistry is based on hexafluorobutadiene (C4F6), a hydrogen-free fluorocarbon that has a low F/C ratio of 1.5. Octafluorocyclopentene (C5F8) has a somewhat higher F/C ratio of 1.6 but still offers many of the same advantages. Octafluorocyclobutane (C4F8) is commonly used in the industry, but its F/C ratio of 2.0 is disadvantageously high for etching vias with very high aspect ratios. During a plasma etch performed under the correct conditions, the fluorocarbon forms a protective polymer on the vertical sidewalls and on bottom non-oxide surfaces of the hole being etched. Thereby, the etch can form vertical sidewalls and be selective to underlying silicon or silicon nitride.
In U.S. patent application Ser. No. 09/522,374, filed Mar. 10, 2000, now issued as U.S. Pat. No. 6,451,703, and incorporated herein by reference in its entirety, Liu et al. describe plasma oxide etch of oxide performed in the magnetically enhanced reactive ion etch (MERIB) reactor 30 schematically illustrated in FIG. 3. Such a reactor is the eMax reactor commercially available from Applied Materials of Santa Clara, California. It includes a grounded vacuum chamber 32, perhaps including liners to protect the walls. A wafer 34 is inserted into the chamber 32 through a slit valve opening 36 and placed on a cathode pedestal 38 with an electrostatic chuck 40 selectively clamping the wafer. The chuck powering is not illustrated. Unillustrated fluid cooling channels through the pedestal 38 maintain the pedestal at reduced temperatures. A thermal transfer gas such as helium is supplied to unillustrated grooves in the upper surface of the pedestal 38 facing the back side of the wafer 34. The thermal transfer gas increases the efficiency of thermal coupling between the temperature controlled pedestal 38 and the wafer 34, which is held against the pedestal 38 by the electrostatic chuck 40 or an alternatively used peripheral wafer clamp.
An RF power supply 42, preferably operating at 13.56 MHz, is connected to the cathode pedestal 38 and provides the only significant power for generating the plasma while it also controls the DC self-bias. Electromagnetic coils 44 positioned at the four sides of the chamber and powered by unillustrated current supplies generate a slowly rotating (on the order of no more than a few seconds and typically somewhat less than 10 ms), horizontal, essentially DC magnetic field in order to increase the density of the plasma. A vacuum pump system 46 pumps the chamber 32 through an adjustable throttle valve 48. Shields 50, 52 not only protect the chamber 32 and pedestal 38 but also define a baffle 54 and a pumping manifold 56 connected to the throttle valve 48.
Processing gases are supplied from gas sources 58, 60, 62, 64 through respective mass flow controllers 66, 68, 70, 72 to a quartz gas distribution plate 74 positioned in the roof of the chamber 32 overlying the wafer 34 and separated from it across a processing region 76. The distribution plate 74 includes a inlet manifold 78 receiving the processing gas and communicating with the processing region 76 through a showerhead having a large number of distributed apertures 80 so as to inject a more uniform flow of processing gas into the processing region 76.
Liu et al. are concerned primarily with the difficult task of etching high aspect-ratio via holes with high selectivity to photoresist and silicon nitride. They accomplish the via etch with an etching gas comprising C4F6, oxygen gas (O2), and a large amount of argon (Ar). The oxygen is used to reduce the amount of polymer produced by C4F6 during the plasma etch. Excessive polymerization causes the sidewall plasma to bridge the developing hole and to prevent further etching of the hole. This deleterious effect is called etch stop.
Liu et al. do not address the BARC open step of removing the thin anti-reflection coating. However, the BARC open, if required, is easily accomplished with a short etch of carbon tetrafluoride (CF4), preferably with no magnetic field. This step is often referred to as the flash step because of its brevity, typically no more than 10 s. Little anisotropy is needed, and no polymer is required in the flash step.
It has been conventional practice to separate the flash step from the main etch by a distinct transition step. After the BARC layer has been opened, the RF power is turned off, thereby extinguishing the plasma, and the supply of CF4 is cut off. Then, the main etch gases of C4F6, O2, and Ar are supplied into the chamber and allowed to equilibrate for about 10 s in achieving the desired pressure. Thereafter in the conventional process, the RF power is turned back on to again excite the plasma and perform the main oxide etch. Typically, it requires about 3 to 5 s to turn on the RF power and reignite the plasma, and another 10 s may be required to equilibrate the chamber if there is a change in pressure or gas composition.
Although such a process has been highly effective in etching the narrow via holes, it has been observed to deleteriously affect the open pads. In particular, as illustrated in the structure of FIG. 4, following the BARC open, a residue 84 tends to form on the oxide 16 at the bottom of the developing open pad. Under severe conditions, the residue 84 prevents further etching and a shallow open pad 86 is formed at the end of etching even though the via holes 24 are completely etched through the oxide layer 14. That is, the dielectric 12 is not etched through in the area of the open pad in a process similar to etch stop. Nonetheless, the narrow contact and via holes 22 are successfully etched. Any etch rates measured with residue forming in the open pad area are nearly useless in correlating etch rates for the via and etch holes 22 from the observed depth of the shallow open pad 86.
In a dielectric plasma etching process, a flash step precedes a main etch step, and the plasma is not extinguished between the flash and main etch steps. The main etch step may be performed using an etching gas including a perfluorocarbon with a low F/C ratio of 1.6 or less, for example, C4F6. The flash step uses a process gas that is less polymerizing than the etching gas. It may be substantially composed of fluorocarbon such as CF4 or of Ar. Other fluorocarbons less polymerizing than the main etchant may be used for the flash step, for example, C4F8 or other perfluorocarbons with an F/C ratio of at least 2.0.
If the dielectric is covered with an anti-reflection coating, the flash step may be used to etch through the anti-reflection coating, for example, with a fluorocarbon etch chemistry.
In another embodiment, a combination of the perfluorocarbon, oxygen, and argon are used in both steps but the ratio of oxygen to perfluorocarbon is higher in the flash than in the main etch step.
The transition from flash to main etch may be shortened by maintaining a same pressure in the etch chamber during the two steps. In a magnetically enhanced plasma reactor with a variable magnetic field, the magnetic field may be turned on only after the transition to the main etch conditions have been achieved, or alternatively increased from a lower value.
The invention is particularly useful for avoiding residue in large open pad areas used for monitoring the process of etching small, high aspect-ratios vias and contact holes. A power-on transition is one of several methods available to maintain a higher temperature in the transition to thereby prevent the residue from depositing.